Function Unit Clustering in Wide-Issue Superscalar Processors

As more function units are integrated into wideissue superscalar processors and as cycle times decrease, result-forwarding delays will become worse relative to processor cycle time. Physical distance and capacitive effects of smaller geometry wires are the main reason for this increase in delay. Thus, a full bypass network, able to forward results from any function unit to any other function unit, cannot be realized without increasing the cycle time. Since increasing the cycle time is undesirable, this paper examines clustering of function units as an approximation to an ideal design where there is no inter-function unit communication delay. A cluster of function units is simply a grouping of neighboring function units with fast intra-cluster communication delay. Communication between clusters is assessed a higher penalty because of the distance between the clusters. This complicates function unit selection over the ideal case where there is no delay between function units. The goal of this work is to examine the performance of a clustered microengine compared with an ideal one with the same function unit resources but no communication delay between function units. The results presented in this paper show that clustered configurations of function units can perform competitively with an ideal non-clustered configuration. It is also shown that the steering heuristic makes a significant difference in performance in some cases, particularly when the inter-cluster bypass delay is high.